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NCP5010
DETAIL OPERATING DESCRIPTION
V Bat
2.7 to 5.5 V
L
C in
1 m F, 6.3 V X5R 0603
V IN
B1
22 m H
C2
SW
A1
AGND
UVLO
OVP
?
COMP
UVLO
COMP
OVP
+
UVLO REF
+
M DUTY REF
MAX DUTY
CYCLE COMP
?
MAX D
THERMAL
PROTECTION
?
OVP REF
V OUT
C1
FB
B3
FB REF
?
ERROR
AMP
+
+
?
PWM
COMP
RST
DRIVER
C out
1 m F
25 V
X5R 0805
+
RAMP
COMP
SET
SHORT
CIRCUIT
PROTECTION
ONE
SHOT
OSC
1 Mhz
CTRL
A2
IPEAK MAX
250 k
+
IPEAK
COMP
?
IPEAK MAX
SENSE
CURRENT
PGND
C3
V IN
R FB
Figure 22. Functional Block Diagram
Operation
The NCP5010 DC?DC converter is based on a Current
Mode PWM architecture which regulates the feedback
voltage at 500 mV under normal operating conditions. The
boost converter operates in two separate phases (See
Figure 23). The first one is T ON when the inductor is
charged by current from the battery to store up energy,
followed by T OFF step where the power is transmitted
through the internal rectifier to the load. The capacitor
C OUT is used to store energy during the T OFF time and to
supply current to the load during the T ON stage thus
constantly powering the load.
The internal oscillator provides a 1 MHz clock signal to
trigger the PWM controller on each rising edge (SET signal)
which starts a cycle. During this phase the low side NMOS
switch is turned on thus increasing the current through the
inductor. The switch current is measured by the SENSE
CURRENT and added to the RAMP COMP signal. Then
PWM COMP compares the output of the adder and the signal
from ERROR AMP. When the comparator threshold is
exceeded, the NMOS switch is turned off until the rising edge
of the next clock cycle. In addition, there are six functions
which can reset the flip?flop logic to switch off the NMOS.
The MAX DUTY CYCLE COMP monitors the pulse width
SW
Start
Cycle
and if it exceeds 95% (nom) of the cycle time the switch will
be turned off. This limits the switch from being on for more
than one cycle. Due to IPEAK COMP, the current through the
1 MHz
I peak
inductor is monitored and compared with the I PEAK_MAX
threshold set at 440 mA (nom). If the current exceeds this
IL
T on
T off
I valley
value, the controller is will turn off the NMOS switch for the
remainder of the cycle. This is a safety function to prevent any
excessive current that could overload the inductor and the
power stage. The four other safety circuits are SHORT
I SW
I out
Figure 23. Basic DC?DC Operation
CIRCUIT PROTECTION, OVP, UVLO, and THERMAL
PROTECTION. Please refer to the detail in following
sections.
The loop stability is compensated by the ERROR AMP
built in integrator. The gain and the loop bandwidth are
fixed internally and provides a phase margin greater than
45 ° whatever the current supplied.
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